USR-ES1 embeds W5500 chip, uses hardware logic gate circuit to realize the transport layer and network layer of TCP/IP protocol stack (such as: TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE and other protocols), and integrates The data link layer, physical layer, and 32K bytes of on-chip RAM are used as data sending and receiving buffers. The main control chip of the host computer only needs to undertake the processing task of the control information of the TCP/IP application layer. This greatly saves the workload of the host computer for data replication, protocol processing and interrupt processing, and improves system utilization and reliability.

During the operation, the user can use the W5500 as a peripheral RAM of the MCU, which is very easy. The external interface of W5500 is a general 80MHz high-speed SPI, which can be used by different platforms to expand high-speed Ethernet solutions. The auto-negotiation LED status shows that the SPI interface is fast and stable.

Features:

• 80MHz high-speed SPI interface
• Built-in hardware TCPIP protocol stack, users hardly need to master complex network protocol knowledge
• Support up to 8 Socket connections
• Support TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE protocols
• Integrated data link layer, physical layer
• Support power-down wake-up
• Support high-speed serial peripheral interface (SPI mode 0~3)
• Internal 32K bytes transceiver buffer
• Embedded 10BaseT/100BaseTX Ethernet physical layer (PHY)
• Support auto-negotiation (10/100-Based full duplex/half duplex)
• Does not support IP fragmentation
• 12.3.3V working voltage, I/O signal port 5V withstand voltage
• LED status display (full duplex/half duplex, network connection, network speed, activity status)
• Ultra-small pin package, easy for embedded applications
• Provide application routines for C